1. Field of the Invention
This invention relates to a method for reordering a scan chain and, more particular, to a method for reordering a scan chain that minimizes the peak power consumption of Very Large Scale Integration (VLSI) Circuits.
2. Description of Related Art
Along with VLSI Circuits designed to be more complex, higher density transistors and lower power consumption components are used widely. Designing a lower power consumption VLSI circuit is the latest trend.
In recent years, a topic for discussion of the Design for Testability (DFT) of VLSI circuits against the power dissipation has been widely regarded. A general designed circuit is operated in two modes: Normal Mode and Test Mode. In the test mode, the test patterns for testing combinatory logic circuits are stored in the scan register of the system. Some of the test patterns may not appear in the normal mode at all. In other words, the potential conversion of the register may not happen in the normal mode and possibly may happen in the test mode. Therefore, the test pattern in the test mode will lead to high power dissipation in the circuit of the register. In another aspect, the test pattern is generated by an Automatic Test Pattern Generator (ATPG) that is designed with DFT and will test the majority of circuits as it possibly can and make the potential of the circuits frequently convert, thereby causing the condition circuit to be more deteriorated.
It is noteworthy that an oversized peak value of power dissipation will lead to a malfunction of the circuit during testing. Namely, a chip normally operating in the normal mode may not be qualified by ATPG. There are various ways of improvement of reducing the power dissipation in the testing mode. Some conventional technologies (R. M. Chou, K. K. Saluja, and V. D. Agrawal, “Scheduling tests for VLSI systems under power constraints,” IEEE Trans. VLSI, vol. 5, no. 2, pp. 175–184, 1997 and S. Wang and S. K. Gupta, “ATPG for heat dissipation minimization during test application,” in Proc. IEEE mt. Test Conf., 1994, pp. 250–257) are used ATPG to create the optimum test patterns capable of reducing the power dissipation.
Further, re-ordering the Scan Chain register can also effectively reduce the power dissipation at the time of the potential conversion. As shown in FIG. 1A, if the test pattern data, 0101, is input to a 4-bit scan chain, ABCD, then 10 times of the potential state conversion occur in the course of 4 times of shift wherein the potential state conversion of each bit occurs in the case of the last shift. If the re-ordered scan chain is BDAC, as shown in FIG. 1B, only 2 times of potential state conversion occur in the course of 4 times of shifts. A conventional technology (V Dabholkar, S. Chakravarty, I. Pomeranz, and S. Reddy, “Techniques far minimizing power dissipation in scan and combinational circuits during test application,” IEEE Trans. CAD, vol. 17, no. 12, pp. 1325–1333, 1998) provides two algorithms: Random Ordering and Simulated Annealing. However, if there is much test pattern data and there are large amounts of registers, ordering of a large number of registers is necessary so as to highly reduce the power dissipation as much as possible, thereby causing uneconomical situations. However, simulated annealing an initial state that is possibly close to minimum power dissipation (otherwise it may take long time to perform the algorithm) is not practical. Regarding this problem, this invention provides research on scan chain ordering that quickly meets the limits of design specifications. Also, still another conventional technology (O. Sinanoglu, I. Bayraktaroglu, and A. Orailoglu, “Scan power reduction through test data transition frequency analysis,” in Proc. Int. Test Conf, 2002, pp. 844–850) is provided to insert an inverter into the parts of the positions of the scan chain, thereby reducing the probability of the potential conversion for a reduction of power dissipation. However, the insertion of the inverter will change the circuit placement formerly completed in the physical design of the VLSI circuit, so that this practice is not involved in the research field of this invention. Next, another conventional technology (S. Ghosh, S. Basu, and N. A. Touba, “Joint minimization of power and area in scan testing by scan cell reordering,” in Proc. IEEE Computer Society Annual Symposium on VLSI, 2003, pp.) seeks for an optimum scan chain ordering using a Greedy Algorithm and considers the connection distance between the power dissipation and the registers. Supposing that the coordinates of the two registers are (x1, y1) and (x2, y2), respectively, |x1−x2|+y1−y2| is given for a Manhattan Distance between the two registers.
In addition to the two conditions, as mentioned above, the limitations of the total connection length of the scan chain, namely, the total length of distance between registers, is considered. Again, seeing from the technologies hereinbefore, a fixed value is given for the power dissipation of each of the two registers in the scan chain and, hence, to reduce the peak value of the power dissipation by cutting down the number of times of the potential state conversion. It is considered in the present invention that the practical power dissipation value of the register is not fixed, so that a small number of times of potential state conversion will not necessarily mean a small power dissipation.